1. Field of the Invention
The present invention relates generally to sense amplifiers, and more specifically to an improved data comparing sense amplifier for use in tag RAMs.
2. Description of the Prior Art
Cache memories are important elements of a typical cache system, and may be used as primary caches embedded in high performance microprocessors or as secondary caches external to the microprocessor. As microprocessors have achieved faster operating speed, the rate at which requested data must be supplied to them has corresponding increased. Cache memories typically have faster access times than main memory and thus are often used to quickly supply data requested by the microprocessor.
Tag RAMS form a key element of the typical cache system. The tag associated with a "line" of data, a block of data which can be one or several consecutive bytes or words of data, in the cache memory is stored in a tag RAM which holds the address locations of data stored in the cache memory. The tag RAM often has a valid bit which indicates whether data stored at a particular address location is valid or invalid. When the microprocessor requests information, a read signal is sent to both the main memory and the tag RAM. The tag RAM compares the requested memory address with the memory address of all data stored in the cache memory. If the requested memory address is in the tag RAM, a "hit" condition exists, and data from that location is gated from the cache memory to the microprocessor.
In a "hit" condition, the tag RAM generates a valid compare Match output signal and the cache memory gates the required data onto the data bus before the main memory can respond. In this way, the cache memory quickly supplies data to the microprocessor and microprocessor wait states are avoided. However, if the tag RAM's comparison operation indicates that the desired data is not stored in the cache memory, a "miss" condition exists, and the data must be supplied from the slower main memory. As a result, the microprocessor may have to idly wait several cycles before it receives the requested data. These unproductive cycles are referred to as "wait states".
As the above discussion on tag RAMs indicates, the compare circuitry of a tag RAM generates a compare Match output signal indicative of whether a "hit" or a "miss" condition exists. Typically, the tag RAM compare circuitry utilizes a sense amplifier in conjunction with one or more logic gates external to the sense amplifier to generate the match output signal. The sense amplifier takes an appropriate bit of an address contained in the cache memory and generates a data output signal. This data output signal is input to a subsequent logic gate, such as a XOR or XNOR gate, where it is gated with the corresponding bit of the address sought by the microprocessor. The output signal of the logic gate is a compare signal indicative of whether a bit of an address requested by the microprocessor matches a corresponding bit of an address stored in the cache memory. There are a plurality of sense amplifiers and associated external logic gates equal to the number of bits of the address sought by the microprocessor. While this scheme of sensing whether the cache memory has the requested data works quite well, the logic gate external to a sense amplifier represents an additional stage with attendant delay. Therefore, according to this method, there will be a delay associated with the sense amplifier as well as a delay associated with the external logic gate. These delays are undesirable, because they increase the time required for the tag RAM to generate the match output signal.